HPC Wire

Subscribe to HPC Wire feed
Since 1987 - Covering the Fastest Computers in the World and the People Who Run Them
Updated: 11 hours 54 min ago

IBM Releases New Compilers to Exploit POWER9 Technology

Fri, 12/15/2017 - 10:04

Dec. 15, 2017 — On Dec 15, IBM released new compilers, XL C/C++ for Linux V13.1.6 and XL Fortran for Linux V15.1.6, to support the latest Power Systems server AC922 and NVIDIA GPU Volta. 

Image courtesy of IBM.

“The new C/C++ and Fortran compilers provide full exploitation of POWER9 technology for industry-leading performance and optimize HPC and Cognitive workloads through GPU acceleration, and is ideal for HPC clients, scientists, and AI leads,” says IBM. 

The POWER9 exploitation features, including a number of new POWER9 built-in functions and high-performance libraries tuned for POWER9, allow the development of optimized applications that utilize the latest POWER9 technology.

The IBM XL compilers’ support for OpenMP 4.5 is enhanced in this new release – new SIMD directives are added and functionality for existing directives is expanded to provide further exploitation and effective programming on GPU.

CUDA Fortran support is also improved to provide better performance for kernels, more functions and customized GPU configurations.

“With the best overall optimization for both CPU & GPU, XL Compilers are positioned as the performance-driven compiler brand on Power Systems to unlock HPC & Cognitive workloads. XL compilers are the ultimate choice to solve massive, complex computing tasks,” said the offering manager of IBM XL compilers.

Other key features of XL C/C++ for Linux V13.1.6 and XL Fortran for Linux V15.1.6 include:

  • Adoption of Clang V4.0 frond-end technology – XL C/C++ for Linux adopts Clang V4.0 frond-end technology, which provides a large degree of compatibility with GCC. Migration to XL C/C++ for Linux is now easy and seamless. More C++14 language features are supported, such as binary integer literals, digit separators, relaxing constraints on constexpr functions, return type deduction for normal functions, etc.
  • OpenMP interoperability with CUDA C/C++ and CUDA Fortran – Development of more portable applications is enabled by calling kernels written in CUDA C/C++ or CUDA Fortran in OpenMP programs from the host.
  • Support for CUDA Toolkit 9.0 and 9.1 – Support for the CUDA Toolkit has been upgraded to CUDA Toolkit version 9.0 and 9.1. The sm_70 and compute_70 GPU architectures are supported as defined by the CUDA Toolkit.
  • Specification of GPU architectures for the generated code – The new -qtgtarch option allows specifying the real or virtual GPU architectures where the code can run, overriding the default GPU architecture. The compiler can take maximum advantage of the capabilities and machine instructions which are specific to a GPU architecture, or common to a virtual architecture.
  • Support for the cuda-memcheck tool – A new environment variable is provided to control whether to disable the check for pinned memory in the runtime and allow the program to be executed under the cuda-memcheck tool from the NVIDIA CUDA Toolkit.
  • Pass LLVM IR bitcode libraries to llvm2ptx – LLVM IR bitcode libraries, which have a suffix of .bc, can be specified on the command line, to pass the LLVM IR bitcode libraries to llvm2ptx, the NVVM-IR to PTX translator.
  • GPU runtime inlining support for inlining calls made to the OpenMP GPU runtime libraries – This enhancement reduces overhead and significantly improves performance of OpenMP target regions that are offloaded to the accelerator.
  • Improved GPU code generation – This enhancement applies to several OpenMP directives when contained in an OpenMP target region, most notably parallel loops and reductions.

For a complete list of new XL compilers features, navigate to “What’s new” from XL C/C++ for Linux V13.1.6 documentation and XL Fortran for Linux V15.1.6 documentation on IBM Knowledge Center.

Download no-charge Community Edition and get started

The no-charge XL C/C++ for Linux and XL Fortran for Linux Community Editions are refreshed with all new functionalities, and allow for unlimited production use. They can be downloaded from the XL C/C++ for Linux and XL Fortran for Linux Marketplace website. The XL C/C++ for Linux and XL Fortran for Linux documentation on IBM Knowledge Center can guide new users through installation and basic compilation tasks. Though no official support is offered with the Community Edition, IBM compilers experts answer users’ feedback to the Community Edition raised at the XL on POWER Fortran Community Edition forum (ibm.biz/xl-power-compilers) to help users solve problems. 

Source: IBM

The post IBM Releases New Compilers to Exploit POWER9 Technology appeared first on HPCwire.

BP Supercomputer Now World’s Most Powerful for Commercial Research

Fri, 12/15/2017 - 09:49

HOUSTON, Dec. 15, 2017 — BP announced today that it has more than doubled the total computing power of its Center for High-Performance Computing (CHPC) in Houston, making it the most powerful supercomputer in the world for commercial research.

Increased computing power, speed and storage reduce the time needed to analyze large amounts of seismic data to support exploration, appraisal and development plans as well as other research and technology developments throughout BP.

“Our investment in supercomputing is another example of BP leading the way in digital technologies that deliver improved safety, reliability and efficiency across our operations and give us a clear competitive advantage,” said Ahmed Hashmi, BP’s head of upstream technology.

The Center for High-Performance Computing provides critical support to BP’s upstream business segment, where it serves as the worldwide hub for research computing. BP’s computer scientists and mathematicians at the CHPC have enabled industry breakthroughs in advanced seismic imaging and rock physics research to help with reservoir modelling.

BP’s downstream business also is using the supercomputer for fluid dynamic research to study hydrocarbon flows at refineries and pipelines to improve operational safety.

Working with Hewlett Packard Enterprise and Intel using HPE’s Apollo System and Intel’s Knights Landing processors, the recent upgrade has boosted the processing speed of BP’s supercomputer from four petaflops to nine petaflops. A petaflop of processing speed is one thousand trillion floating point operations, or “flops,” per second.

The supercomputer has a total memory of 1,140 terabytes (1.14 petabytes) and 30 petabytes of storage, the equivalent of over 500,000 iPhones.

“With the expansion and new systems in place, BP will be able to further bolster its capabilities to accurately process and manage vast amounts of seismic data to identify new business opportunities and improve operational efficiency,” said Alain Andreoli, senior vice president and general manager, Data Center Infrastructure Group, Hewlett Packard Enterprise.

Since the CHPC opened in 2013, BP has quadrupled its computing power and doubled its storage capacity and plans to continue expanding its computing capability in 2018.

About BP

BP is a global producer of oil and gas with operations in over 70 countries. Over the past 10 years, BP has invested $90 billion in the U.S. – more than any other energy company. BP employs about 14,000 people across the U.S. and supports more than 106,000 additional jobs through all its business activities. For more information on BP in the U.S., visit www.bp.com/us.

Source: BP

The post BP Supercomputer Now World’s Most Powerful for Commercial Research appeared first on HPCwire.

Mont-Blanc 2020 Project Looks to Pave the Way for New European Exascale Processors

Fri, 12/15/2017 - 09:36

LES CLAYES, France, Dec. 15, 2017 — Following on from the three successive Mont-Blanc projects since 2011, the three core partners Arm, Barcelona Supercomputing Center and Bull (Atos Group) have united again to trigger the development of the next generation of industrial processor for Big Data and High Performance Computing. The Mont-Blanc 2020 consortium also includes CEA, Forschungszentrum Jülich, Kalray, and SemiDynamics.

The Mont-Blanc 2020 project has a budget of 10.1 million Euros, funded by the European Commission under the Horizon2020 program. It was launched on 11th December at the Atos site in Les Clayes (France), with a kick-off meeting that gathered representatives of all partners.

Image courtesy of Mont-Blanc 2020.

The Mont-Blanc 2020 project intends to pave the way to the future low-power European processor for Exascale. To improve the economic sustainability of the processor generations that will result from the Mont-Blanc 2020 effort, the project includes the analysis of the requirements of other markets. The project’s strategy based on modular packaging would make it possible to create a family of SoCs
targeting different markets, such as “embedded HPC” for autonomous driving. The project’s actual objectives are to:

  • define a low-power System-on-Chip architecture targeting Exascale;
  • implement new critical building blocks (IPs) and provide a blueprint for its first generation implementation;
  • deliver initial proof-of-concept demonstration of its critical components on real life applications;
  • explore the reuse of the building blocks to serve other markets than HPC, with methodologies enabling a better time-predictability, especially for mixed-critical applications where guaranteed execution & response times are crucial.

The project will have to tackle three key challenges to achieve the desired performance with the targeted power consumption:

  1. understand the trade-offs between vector length, NoC bandwidth and memory bandwidth to maximize processing unit efficiency;
  2. an innovative on-die interconnect that can deliver enough bandwidth to the processing units, with minimum energy consumption;
  3. a high-bandwidth and low power memory solution with enough capacity and bandwidth for Exascale applications.

“The ambition of the consortium is to quickly industrialize our research. This is why we decided to rely on the Arm instruction set architecture (ISA), which is backed by a strong software ecosystem. By leveraging the current efforts, including the Mont-Blanc ecosystem and other international projects, we will benefit from the system software and applications required for successful usage” explained Said Derradji, Atos, coordinator of the Mont-Blanc 2020 project.

About the Mont-Blanc 2020 project

Mont-Blanc 2020’s goal is to initiate a family of processors that will be the basis for European Big Data / High Performance Computing exascale systems, and that will achieve market adoption and economic sustainability.

The Mont-Blanc 2020 project is run by a European consortium that includes:
Atos / Bull, the European number one in Big Data and High Performance Computing (coordinator, France);

  • Arm, the world’s leading semiconductor IP company (United Kingdom);
  • Barcelona Supercomputing Centre, the national supercomputing centre in Spain;
  • CEA, the French Alternative Energies and Atomic Energy Commission;
  • Forschungszentrum Jülich, one of the largest interdisciplinary research institutions in Europe (Germany);
  • Kalray, a leading innovator with its supercomputing on a chip MPPA solutions (France);
  • SemiDynamics, a specialist in microprocessor architecture, front-end design and verification services (Spain).

This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 779877.

Source: Mont-Blanc 2020

The post Mont-Blanc 2020 Project Looks to Pave the Way for New European Exascale Processors appeared first on HPCwire.

IBM Launches Commercial Quantum Network with Samsung, ORNL

Thu, 12/14/2017 - 10:31

In the race to commercialize quantum computing, IBM is one of several companies leading the pack. Today, IBM announced it had signed JPMorgan Chase, Daimler AG, Samsung and a number of other corporations to its IBM Q Network, which provides online access to IBM’s experimental quantum computing systems. IBM is also establishing regional research hubs at IBM Research in New York, Oak Ridge National Lab in Tennessee, Keio University in Japan, Oxford University in the United Kingdom, and the University of Melbourne in Australia.

IBM Q system control panel (photo: IBM)

Twelve organizations in total will be using the IBM prototype quantum computer via the company’s cloud service to accelerate quantum development as they explore a broad set of industrial and scientific applications. Other partners include JSR Corporation, Barclays, Hitachi Metals, Honda, and Nagase.

Partners currently have access to the 20 qubit IBM Q system, which IBM announced last month, but Big Blue is also building an operational prototype 50 qubit processor, which will be made available in next generation IBM Q systems. The partners will specifically be looking to identify applications that will elicit a quantum advantage, such that they perform better or faster on a quantum machine than a classical one.

IBM leadership believes we are at the dawn of the commercial quantum era. “The IBM Q Network will serve as a vehicle to make quantum computing more accessible to businesses and organizations through access to the most advanced IBM Q systems and quantum ecosystem,” said Dario Gil, vice president of AI and IBM Q, IBM Research in a statement. “Working closely with our clients, together we can begin to explore the ways big and small quantum computing can address previously unsolvable problems applicable to industries such as financial services, automotive or chemistry. There will be a shared focus on discovering areas of quantum advantage that may lead to commercial, intellectual and societal benefit in the future.”

Experts from the newly formed IBM Q Consulting will be able to provide support and offer customized roadmaps to help clients become quantum-ready, says IBM.

With IBM Q, IBM seeks to be the first tech company to deliver commercial universal quantum computing systems for and in tandem with industry and research users. Although today marks the start of its commercial network, IBM has been providing scientists, researchers, and developers with free access to IBM Q processors since May 2016 via the IBM Q Experience. According to the company, 60,000 registered users have collectively run more than 1.7 million experiments and generated over 35 third-party research publications.

To see some really cool photos of IBM’s quantum computing technology, check out their flickr stream here (it’s really not to be missed).

The post IBM Launches Commercial Quantum Network with Samsung, ORNL appeared first on HPCwire.

Lenovo and Intel to Deliver Next-Generation Supercomputer to Leibniz Supercomputing Center

Thu, 12/14/2017 - 09:21

RESEARCH TRIANGLE PARK, N.C., Dec. 14, 2017 — Lenovo (SEHK:0992) (Pink Sheets:LNVGY) Data Center Group and Intel will deliver a next-generation supercomputer to Leibniz Supercomputing Centre (LRZ) of the Bavarian Academy of Sciences in Munich, Germany. One of the foremost European computing centers for professionals in the scientific, research and academic communities, LRZ is tasked with managing not only exponential amounts of big data, but processing and analyzing that data quickly to accelerate research initiatives around the world. For example, the LRZ recently completed the world’s largest simulation of earthquakes and resulting tsunami’s, such as the Sumatra-Andaman Earthquake. This research enables real-time scenarios planning that can help predict aftershocks and other seismic hazards.

Upon its completion in late 2018, the new supercomputer (called SuperMUC-NG) will support LRZ in its groundbreaking research across a variety of complex scientific disciplines, such as astrophysics, fluid dynamics and life sciences, by offering highly available, secure and energy-efficient high-performance computing (HPC) services that leverage industry-leading technology optimized to address the a broad range of scientific computing applications. The LRZ installation will also feature the 20-millionth server shipped by Lenovo, a significant milestone in the company’s data center history.

“Lenovo is committed to providing research institutions like LRZ with not only sheer computing power, but a true, end-to-end solution that can help effectively and efficiently solve critical humanitarian challenges. We’re pleased to be working on this next-generation project in partnership with Intel,” said Scott Tease, Executive Director, HPC and AI, Lenovo Data Center Group. “The new SuperMUC-NG installation will provide LRZ with greater compute power in a smaller data center footprint with drastically reduced energy usage through innovative water-cooling technology, offering researchers a comprehensive supercomputing solution that packs more performance than ever to accelerate critical research projects.”

The SuperMUC-NG will deliver a staggering 26.7 petaflop compute capacity powered by nearly 6,500 nodes of Lenovo’s recently-announced, next-generation ThinkSystem SD650 servers, featuring Intel Xeon Platinum processors with Intel Advanced Vector Extensions (Intel AVX 512), and interconnected with Intel Omni-Path Architecture. The new system will also include the integration of Lenovo Intelligent Computing Orchestrator (LiCO), a powerful management suite with an intuitive GUI that helps accelerate development of HPC and AI applications, as well as cloud-based components to empower LRZ researchers with the freedom to virtualize, process the vast amount of data sets and expediently share results with colleagues.

To address the often-astronomical operational expenses generated by high-performance computing (HPC) infrastructure, the new SuperMUC-NG supercomputer will benefit from Intel technical optimizations and also feature cutting-edge water cooling technology from Lenovo. In combination with Lenovo Energy Aware Run-Time (EAR) software, a technology that dynamically controls system infrastructure power while applications are still running, Lenovo’s comprehensive water-cooling technology delivers 45 percent greater electricity savings to LRZ as compared to a similar, standard air-cooled system. Together, these energy efficiency innovations will help further reduce the research center’s carbon footprint and total cost of ownership.

“Global research leaders like LRZ are driving insights that address not only some of the most complex problems we face, but that also make meaningful improvements in all of our lives,” said Trish Damkroger, Vice President of Technical Computing at Intel. “Intel offers the technical foundation that, when combined with the solution expertise of Lenovo, delivers the efficient performance and ease of programing to help LRZ’s researchers drive more discoveries with deeper analytics than have ever been possible before.”

Once operational, the LRZ SuperMUC-NG system is expected to place on the industry-wide TOP500 list.

About Lenovo

Lenovo (SEHK:0992) (Pink Sheets:LNVGY) is a US$43 billion global Fortune 500 company and a leader in providing innovative consumer, commercial, and data center technology. Our portfolio of high-quality, secure products and services covers PCs (including the legendary Think and multimode Yoga brands), workstations, servers, storage, networking, software (including ThinkSystem and ThinkAgile solutions), smart TVs and a family of mobile products like smartphones (including the Motorola brand), tablets and apps. Join us on LinkedIn, follow us on Facebook or Twitter (@Lenovo) or visit us at http://www.lenovo.com/.

Source: Lenovo

The post Lenovo and Intel to Deliver Next-Generation Supercomputer to Leibniz Supercomputing Center appeared first on HPCwire.

Second Industry-Wide, Multi-Vendor Plugfest Focused on NVMe Over Fibre Channel Fabric Completed by Fibre Channel Industry Association

Wed, 12/13/2017 - 13:48

MINNEAPOLIS, Dec. 13, 2017 — The Fibre Channel Industry Association (FCIA) today announced the completion of its second industry-wide multi-vendor plugfest focused on Non-Volatile Memory Express  (NVMe) over Fibre Channel (FC) Fabric and the first validation of the newly completed INCITS T11 FC-NVMe standard.

FCIA’s FC-NVMe plugfest was held during the NVM Express organization’s management interface (NVMe-MI) plugfest, the week of October 30, 2017, at the University of New Hampshire InterOperability Lab (UNH-IOL).  An independent provider of broad-based testing and standards conformance services for the networking industry, UNH-IOL has conducted more than 38 plugfests with FCIA over 18 years to test the continued development of FC technologies.

“The completion of this second FC-NVMe plugfest comes at a critical junction,” said FC-NVMe plugfest participant Mark Jones, president and chairman of the board, FCIA, and director, Technical Marketing and Performance, Broadcom Limited. “Major operating system vendors are just releasing support for NVMe over Fabrics and the FC-NVMe INCITS T11 standard is now complete and has been forwarded to INCITS. The FC-NVMe technology is on track to becoming as interoperable and reliable as previous generations of FC, while vastly improving performance for the next generation all-flash datacenters.”

With nine companies participating, the FCIA’s FC-NVMe plugfest featured conformance, error injection, multi-hop, and interoperability testing of FC-NVMe concurrently with Gen 6 32GFC and previous FC generation fabric switches and directors, utilizing datacenter-proven test tools and test methods.

Key accomplishments from this second FCIA-sponsored plugfest of FC-NVMe include:

  • Multiple vendor FC-NVMe initiator, switch, and target conformance and interoperability
  • Gen 6 16 and 32GFC fabric connectivity to a variety of market available NVMe drives
  • Data integrity validation over multi-vendor direct-connect and switched multi-hop fabric topologies
  • Error injection tests to validate correct FC-NVMe and FC recovery and data integrity
  • Concurrent NVMe and legacy SCSI traffic through the same FC fabric ports
  • FC-NVMe and FC over 32GFC long wave 10km single mode fiber inter-switch trunked ports
  • FC-NVMe packet inspection conformance analysis using advanced trace capture and analysis tools
  • Cross fabric inline trace based relative performance comparisons of FCP-SCSI and FC-NVMe
  • Multi-vendor high availability multi-speed concurrent FC-NVMe and FC fabric conformance and interoperability
  • Trials of the UNH-IOL’s NVMe over Fabrics conformance test suite of products for inclusion on the NVMe Integrator’s List

“It is an honor to lead and participate in plugfests with outstanding engineers from across the FC industry who share a single purpose of driving FC-NVMe technology to be interoperable at the highest level of dependability expected by the FC community,” said Barry Maskas, plugfest chair and Technical Staff consultant at Hewlett Packard Enterprise. “In comparison to the first FC-NVMe focused plugfest, results from this second event showed continued maturation demonstrated through tested use case configurations. Plugfest participants refined the validation, certification, and performance characterization foundation which has proven successful by previous FC technology innovations for the benefit of our collective customers.”The nine companies participating in FCIA’s FV-NVMe plugfest were:

  • Amphenol Corporation
  • Brocade Communications Systems, Inc.
  • Broadcom Limited
  • Cisco Systems
  • Hewlett Packard Enterprise
  • QLogic Corporation, a Cavium, Inc. company
  • SANBlaze Technology, Inc.
  • Teledyne Technologies; LeCroy Corporation
  • Viavi Solutions Inc.

“The UNH-IOL has worked with the FCIA and its member companies for over 20 years on Fibre Channel’s latest technological enhancements,” said Timothy Sheehan, manager, Datacenter Technologies, UNH-IOL. “The IOL is focused on supporting the for Non-Volatile Memory Express (NVMe) Fabrics conformance and interoperability testing and has brought this experience to the FCIA member companies. The last two FCIA plugfest events have focused on FC-NVMe testing and have shown great progress.”

About FCIA

The Fibre Channel Industry Association (FCIA) is a non-profit international organization whose sole purpose is to act as the independent technology and marketing voice of the Fibre Channel industry. We are committed to helping member organizations promote and position Fibre Channel, and to provide a focal point for Fibre Channel information, standards advocacy, and education. FCIA members include manufacturers, system integrators, developers, vendors, industry professionals, and end users. Our member-led working groups and committees focus on creating and championing the Fibre Channel technology roadmaps, targeting applications that include data storage, video, networking, and storage area network (SAN) management. For more info, go to http://www.fibrechannel.org.

Source: FCIA

The post Second Industry-Wide, Multi-Vendor Plugfest Focused on NVMe Over Fibre Channel Fabric Completed by Fibre Channel Industry Association appeared first on HPCwire.

NVM Express, Inc. Debuts NVMe Over Fabrics Compliance Testing

Wed, 12/13/2017 - 12:58

BEAVERTON, Ore., Dec. 13, 2017—NVM Express, Inc., the organization that developed the NVM Express (NVMe) and NVMe Management Interface (NVMe-MI) specifications for accessing solid-state drives (SSDs) on a PCI Express (PCIe) bus as well as over Fabrics, hosted its eighth NVMe Plugfest at theUniversity of New Hampshire Interoperability Laboratory (UNH-IOL) in Durham, N.H. during the week of October 30—November 2. The event offered the first official NVMe Over Fabrics (NVMe-oF) compliance and interoperability transport layer testing for RoCE, Remote Direct Memory Access (RDMA) over Converged Ethernet, and the Fibre Channel.

The testing performed by the UNH-IOL, an independent testing provider of standards conformance solutions and multi-vendor interoperability, generated 14 new certified products for the base NVMe Integrators Listand one for the NVMe-MI Integrators List. Eight inaugural products were also approved for the newly launched NVMe-oF Integrators List, which accepts RoCE initiators and targets, Ethernet switches, as well as Fibre Channel initiator, targets and switches, and software.

“Since 2013, the UNH-IOL has certified over 112 NVMe-based products at the NVM Express Plugfests,” David Woolf, senior engineer, Datacenter Technologies at the UNH-IOL, said. “By continuing to prioritize specification compliance and interoperability testing, companies can ensure faster time to market and seamless interactions with other devices NVMe-based solutions.”

Attendance at the NVMe Plugfest included 63 engineers from 19 different companies focused in enterprise, client, cloud storage and test equipment manufacturing. Participating NVM Express member companies included Broadcom, Brocade, Cavium, Cisco, Intel, Lite-On, Mellanox, Microsemi, Oakgate, SANBlaze, Seagate, SerialTek, SK Hynix, Starblaze, Teledyne-LeCroy, Via Technologies, Viavi, Toshiba and Western Digital.

“The growth and success of NVMe Plugfests demonstrate maturing NVM Express technology and a readiness for Fabrics,” Ryan Holmquist, Chair of the NVMe Interoperability and Compliance Committee (ICC), said. “Our testing events have expanded as existing standards evolve, offering a diverse and multiplying set of transports to test NVMe technologies—from PCIe architecture to over SAN, from ROCE or Fibre Channel. Beyond technology growth, the Plugfests foster a collaborative environment for device analyzer, test equipment manufacturers and industry experts to discuss issues and exchange ideas.”

The next NVMe Plugfest will be held in spring 2018 at the UNH-IOL in Durham, N.H.

About NVM Express, Inc.

With more than 100 members, NVM Express, Inc. is a non-profit organization focused on enabling broad ecosystem adoption of high performance and low latency non-volatile memory (NVM) storage through a standards-based approach. The organization offers an open collection of NVM Express (NVMe) specifications and information to fully expose the benefits of non-volatile memory in all types of computing environments from mobile to data center. NVMe-based specifications are designed from the ground up to deliver high bandwidth and low latency storage access for current and future NVM technologies. For more information, visit http://www.nvmexpress.org. The NVM Express Promoter Group is comprised of the following member companies: Cisco, Dell EMC, Facebook, Intel, Micron, Microsemi, Microsoft, NetApp, Oracle, Samsung, Seagate, Toshiba, and Western Digital.

Source: NVM Express, Inc.

The post NVM Express, Inc. Debuts NVMe Over Fabrics Compliance Testing appeared first on HPCwire.

TACC Researchers Test AI Traffic Monitoring Tool in Austin

Wed, 12/13/2017 - 10:47

Traffic jams and mishaps are often painful and sometimes dangerous facts of life. At this week’s IEEE International Conference on Big Data being held in Boston, researchers from TACC and colleagues will present a new deep learning tool that uses raw traffic camera footage from City of Austin cameras to recognize objects – people, cars, buses, trucks, bicycles, motorcycles and traffic lights – and characterize how those objects move and interact.

The researchers from Texas Advanced Computing Center (TACC), the University of Texas Center for Transportation Research and the City of Austin have been collaborating to develop tools that allow sophisticated, searchable traffic analyses using deep learning and data mining. An account of the work (Artificial Intelligence and Supercomputers to Help Alleviate Urban Traffic Problems), written by Aaron Dubrow, was posted this week on the TACC website.

Their work is being tested in parts of Austin where cameras on signal lights automatically counted vehicles in a 10-minute video clip, and preliminary results showed that their tool was 95 percent accurate overall.

“We are hoping to develop a flexible and efficient system to aid traffic researchers and decision-makers for dynamic, real-life analysis needs,” said Weijia Xu, a research scientist who leads the Data Mining & Statistics Group at TACC. “We don’t want to build a turn-key solution for a single, specific problem. We want to explore means that may be helpful for a number of analytical needs, even those that may pop up in the future.” The algorithm they developed for traffic analysis automatically labels all potential objects from the raw data, tracks objects by comparing them with other previously recognized objects and compares the outputs from each frame to uncover relationships among the objects.

The team used the open-source YOLO library and neural network developed by University of Washington and Facebook researchers for real-time object detection. According to the team, this is the first time YOLO has been applied to traffic data. For the data analysis and query component, they incorporated HiveQL, a query language maintained by the Apache Software Foundation that lets individuals search and compare data in the system.

Once researchers had developed a system capable of labeling, tracking and analyzing traffic, they applied it to two practical examples: counting how many moving vehicles traveled down a road and identifying close encounters between vehicles and pedestrians.

“Current practice often relies on the use of expensive sensors for continuous data collection or on traffic studies that sample traffic volumes for a few days during selected time periods,” Natalia Ruiz Juri, a research associate and director of the Network Modeling Center at UT’s Center for Transportation Research. “The use of artificial intelligence to automatically generate traffic volumes from existing cameras would provide a much broader spatial and temporal coverage of the transportation network, facilitating the generation of valuable datasets to support innovative research and to understand the impact of traffic management and operation decisions.”

Whether autonomous vehicles will mitigate the problem is an ongoing debate and Juri notes, “The highly anticipated introduction of self-driving and connected cars may lead to significant changes in the behavior of vehicles and pedestrians and on the performance of roadways. Video data will play a key role in understanding such changes, and artificial intelligence may be central to enabling comprehensive large-scale studies that truly capture the impact of the new technologies.”

Link to full article: https://www.tacc.utexas.edu/-/artificial-intelligence-and-supercomputers-to-help-alleviate-urban-traffic-problems

Link to video on the work: http://soda.tacc.utexas.edu

Images: TACC

The post TACC Researchers Test AI Traffic Monitoring Tool in Austin appeared first on HPCwire.

Supermicro Announces Receipt of Extension from Nasdaq

Wed, 12/13/2017 - 09:14

SAN JOSE, Calif., Dec. 13, 2017 — Super Micro Computer, Inc. (NASDAQ:SMCI), a global leader in high-performance, high-efficiency server, storage technology and green computing, today announced that on December 11, 2017 it had received a letter from the Nasdaq Stock Market (“Nasdaq”) confirming that the Company has been granted an exception to enable the Company to regain compliance with the Nasdaq continued listing requirements. Pursuant to the terms of the exception, on or before March 13, 2018, the Company must file its Annual Report on Form 10-K for the fiscal year ended June 30, 2017 as well as its Quarterly Reports on Form 10-Q for the quarters ended September 30, 2017 and December 31, 2017.

Pursuant to Nasdaq rules, Super Micro’s securities will remain listed on the Nasdaq Global Select Market pending satisfaction of the terms of the exception. In the event the Company does not make the filings within the time period required, Nasdaq will provide written notification that the Company’s securities will be delisted. At that time, the Company may appeal Nasdaq’s determination to a Hearings Panel. Super Micro intends to take all necessary steps to achieve compliance with the Nasdaq continued listing requirements as soon as practicable.

About Super Micro Computer, Inc.

Supermicro, a global leader in high-performance, high-efficiency server technology and innovation is a premier provider of end-to-end green computing solutions for Data Center, Cloud Computing, Enterprise IT, Hadoop/Big Data, HPC and Embedded Systems worldwide. Supermicro’s advanced Server Building Block Solutions® offer a vast array of components for building energy-efficient, application-optimized, computing solutions. Architecture innovations include Twin, TwinPro, FatTwin, Ultra Series, MicroCloud, MicroBlade, SuperBlade, Double-sided Storage, Battery Backup Power (BBP) modules and WIO/UIO.

Source: Super Micro Computer, Inc.

The post Supermicro Announces Receipt of Extension from Nasdaq appeared first on HPCwire.

AMD Wins Another: Baidu to Deploy EPYC on Single Socket Servers

Wed, 12/13/2017 - 06:30

When AMD introduced its EPYC chip line in June, the company said a portion of the line was specifically designed to re-invigorate a single socket segment in what has become an overwhelmingly two-socket landscape in the data center. Today, AMD and Baidu announced that China’s giant internet provider would offer AI, big data, and cloud computing services on EPYC-based single socket solutions.

This deal follows last week’s announcement that Microsoft Azure would offer EPYC-based instances (see HPCwire article, Azure Debuts AMD EPYC Instances for Storage Optimized Workloads). The EPYC line’s high memory bandwidth and IO capacity makes it well suited for many areas but especially for storage servers. AMD is working to ensure EPYC doesn’t become stereotyped by this perception.

“You have probably seen in the industry a fair number of single socket platforms from us but they have tended to be more on the storage optimized or GPU optimized,” said Scott Aylor, AMD corporate vice president and general manager of Enterprise Solutions. For example, HPE introduced a storage optimized server, CL3150, using a single socket EPYC design. “Given the variety of services that Baidu deploys, including storage but also others, I want people to know this is really a compute oriented platform,” said Aylor.

It’s clear AMD is targeting price-performance points that it hopes Intel will find difficult to match and that will help AMD reclaim chunks of the x86 data center market after a lengthy absence. The single socket gambit is an important part of the strategy as was made clear by Aylor at the June launch.

“We can build a no compromise one-socket offering that will allow us to cover up to 50 percent of the two-socket market that is today held by the [Intel Broadwell] E5-2650 and below.

“In our one socket offering we have come up with a clever way to maintain all of the I/O capabilities that you would get in a two socket as well as the full complement of eight memory channels. Today people buy two socket, sometimes because they need to, but more often than not because they have to. There are many examples in which I/O rich [workloads] like storage, like GPU compute, and some vertical workloads where people don’t necessarily need two sockets from a CPU performance perspective,” said Aylor.

AMD contends the EPYC processor will deliver 2.6X the I/O density than competitive[i] solutions and enable Baidu to achieve a level of scale and efficiency unrivaled in high-performance x86. “The combination of performance from the EPYC processor cores, and compute and I/O density packaged in a single-socket configuration, provides the ideal platform for Baidu’s next generation cloud services,” according to AMD.

“By offering outstanding performance in single-processor systems, the AMD EPYC platform provides flexibility and high-performance in our datacenter, which allows Baidu to deliver more efficient services to our customers,” said Liu Chao, senior director, Baidu System Technologies Department in the official release.

Again, from the EPYC launch in June, Aylor said, “We’ve selectively optimized a couple of skews for one socket only. So these are skews that are one socket capable only.” As an example of how the one socket and two socket offerings are distinguished, he cited on package interconnect, “The infinity fabric that would normally connect the two sockets in a two socket system, we repurpose that interconnect into more I/O lanes and that’s how you have in a two socket solution 128 lanes of PCIe and in a one socket solution you still keep the same level of connectivity.”

Today’s announcement punctuates what has been a heady year for AMD. Adoption of the single socket solution by Baidu is another demonstration of market traction and according to AMD, Baidu expects to expand its use of EPYC processors across its global datacenters beginning in the first quarter of 2018.

“This announcement with Baidu and the fact that it is AI, big data, and cloud; those are all computing oriented workloads. So think about the point we raised when we first launched [which] is we now can take what has been part of the mainstream of the market and everything that historically has been the [Intel] E5-2650 and below, and really, looking at the [Skylake] Silver and Gold today from [Intel], we can really address that now with a single socket platform,” said Aylor.

It will be interesting to watch how big a swath AMD’s single socket initiative can cut in the competitive data center market. Aylor said more and more varied single socket EPYC-based offerings are coming, but didn’t specify from who or when.

[i] Information supplied by AMD: AMD EPYCTM processor supports up to 128 PCIe Gen 3 I/O lanes (in both 1 and 2-socket configuration), versus the Intel Xeon SP Series processor supporting a maximum of 48 lanes PCIe Gen 3 per CPU, plus 20 lanes in the I/O chip (max of 68 lanes on 1 socket and 96 lanes on 2 socket). NAP-56

The post AMD Wins Another: Baidu to Deploy EPYC on Single Socket Servers appeared first on HPCwire.

Microsoft Wants to Speed Quantum Development

Tue, 12/12/2017 - 16:13

Quantum computing continues to make headlines in what remains of 2017 as tech giants jockey to establish a pole position in the race toward commercialization of quantum. This week, Microsoft took the next step in advancing its vision for the future of computing that it says will spur major advances in artificial intelligence and address humanities biggest challenges such as world hunger and climate change.

On Monday, Microsoft unveiled its custom Q# (Q-sharp) programming language as part of its effort to build an end-to-end topological quantum computing system suitable for commercial purposes. Along with a simulator for debugging and testing quantum code, Q# is included in Microsoft’s Quantum Development Kit, first announced by the company in September.

“Designed ground up for quantum, Q# is the most approachable high-level programming language with a native type system for qubits, operators, and other abstractions,” says Microsoft. “It is fully integrated with Visual Studio, enabling a complete professional enterprise-grade development tooling system for the fastest path to quantum programming efficiency.”

Using the local quantum simulator on a standard laptop, developers will be able to simulate up to 30 logical qubits, according to Microsoft. For developers who want to go beyond that, Microsoft is offering an Azure-based simulator that supports simulations above 40 logical qubits.

The preview version of the development kit is available at no charge and comes with documentation, libraries and sample programs. Microsoft said that the kit will “give people the background they need to start playing around with aspects of computing that are unique to quantum systems, such as quantum teleportation.”

According to the company, programs created for the simulator will be transferable to a real topological machine, which Microsoft is in the process of developing. Microsoft’s approach to building a universal quantum computer is centered on the topological qubit, purported to be more stable than other qubit implementations. Most approaches to quantum computing require massive amounts of error correction such that a useful device could require 10 physical qubits to achieve one logical qubit, potentially pushing up the number of physical qubits into the tens of thousands. Researchers propose that the topological qubit naturally resists decoherence and therefore requires less error correction. Conceivably this would make it possible to build a quantum machine with fewer physical qubits.

In the video below, Krysta Svore, principal researcher at Microsoft, demonstrates the new Microsoft Quantum Development Kit.

Lots of good info to get started here — https://docs.microsoft.com/en-us/quantum/index?view=qsharp-preview

The post Microsoft Wants to Speed Quantum Development appeared first on HPCwire.

Physicists Win Supercomputing Time to Study Fusion and the Cosmos

Tue, 12/12/2017 - 13:10

Dec. 12, 2017 — More than 210 million core hours on two of the most powerful supercomputers in the nation have been won by two teams led by researchers at the U.S. Department of Energy’s (DOE) Princeton Plasma Physics Laboratory (PPPL). The highly competitive awards from the DOE Office of Science’s INCITE (Innovative and Novel Impact on Computational Theory and Experiment) program will accelerate the development of nuclear fusion as a clean and abundant source of energy for generating electricity and will advance understanding of the high-energy-density (HED) plasmas found in stars and other astrophysical objects.

A single core hour represents the use of one computer core, or processor, for one hour. A laptop computer with only one processor would take some 24,000 years to run 210 million core hours.

“Extremely important and beneficial”

“These awards are extremely important and beneficial,” said Michael Zarnstorff, deputy director for research at PPPL. “They give us access to leadership-class highest-performance computers for highly complex calculations. This is key for advancing our theoretical modeling and understanding.” Leadership-class computing systems are high-end computers that are among the most advanced in the world for solving scientific and engineering problems.

The allocations include more than 160 million core hours for physicist C.S. Chang and his team, marking the first year of a renewable three-year award. The first-year hours are distributed over two machines: 100-million core hours on Titan, the most powerful U.S supercomputer, which can perform some 27 quadrillion (1015) calculations per second at the Oak Ridge Leadership Computing Facility (OLCF); and 61.5 million core hours on Theta, which completes some 10 quadrillion calculations a second at the Argonne Leadership Computing Facility (ALCF).  Both sites are DOE Office of Science User Facilities.

Also received are 50 million core hours on Titan for Amitava Bhattacharjee, head of the Theory Department at PPPL, and William Fox and their team to study HED plasmas produced by lasers.

Chang’s group consists of colleagues at PPPL and other institutions and will use the time to run the XGC code developed by PPPL and nationwide partners.  The team is exploring the dazzlingly complex edge of fusion plasmas with Chang as lead principal investigator of the partnership center for High-fidelity Boundary Plasma Simulation — a program supported by the DOE Office of Science’s Scientific Discovery through Advanced Computing (SciDAC). The edge is critical to the performance of plasma that fuels fusion reactions.

Fusion — the fusing of light elements

Fusion is the fusing of light elements that most stars use to generate massive amounts of energy – and that scientists are trying to replicate on Earth for a virtually inexhaustible supply of energy. Plasma – the fourth state of matter that makes up nearly all the visible universe – is the fuel they would use to create fusion reactions.

The XGC code will perform double-duty to investigate developments at the edge of hot, charged fusion plasma. The program will simulate the transition from low- to high-confinement of the edge of fusion plasmas contained inside magnetic fields in doughnut-shaped fusion devices called tokamaks. Also simulated will be the width of the heat load that will strike the divertor, the component of the tokamak that will expel waste heat and particles from future fusion reactors based on magnetic confinement such as ITER, the international tokamak under construction in France to demonstrate the practicality of fusion power.

The simulations will build on knowledge that Chang has achieved in the previous-cycle SciDAC project.  “We’re just getting started,” Chang said. “In the new SciDAC project we need to understand the different types of transition that are thought to occur in the plasma, and the physics behind the width of the heat load, which can damage the divertor in future facilities such as ITER if the load is too narrow and concentrated.”

Advancing progress in understanding HED plasmas

The Bhattacharjee-Fox award, the second and final part of a two-year  project, will advance progress in the team’s understanding of the dynamics of magnetic fields in HED plasmas. “The simulations will be immensely beneficial in designing and understanding the results of experiments carried out at the University of Rochester and the National Ignition Facility at Lawrence Livermore National Laboratory” Bhattacharjee said.

The project explores the magnetic reconnection and shocks that occur in HED plasmas, producing enormous energy in processes such as solar flares, cosmic rays and geomagnetic storms. Magnetic reconnection takes place when the magnetic field lines in plasma converge and break apart, converting magnetic energy into explosive particle energy. Shocks appear when the flows in the plasma exceed the speed of sound, and are a powerful process for accelerating charged particles.

To study the process, the team fires high-power lasers at tiny spots of foil, creating plasma bubbles with magnetic fields that collide to form shocks and come together to create reconnection. “Our group has recently made important progress on the properties of shocks and novel mechanisms of magnetic reconnection in laser-driven HED plasmas,” Bhattacharjee said. “This could not be done without INCITE support.”

PPPL, on Princeton University’s Forrestal Campus in Plainsboro, N.J., is devoted to creating new knowledge about the physics of plasmas — ultra-hot, charged gases — and to developing practical solutions for the creation of fusion energy. The Laboratory is managed by the University for the U.S. Department of Energy’s Office of Science, which is the largest single supporter of basic research in the physical sciences in the United States, and is working to address some of the most pressing challenges of our time. For more information, please visit science.energy.gov(link is external).

Source: PPPL

The post Physicists Win Supercomputing Time to Study Fusion and the Cosmos appeared first on HPCwire.

ACM Recognizes 2017 Fellows for Advancing Technology in the Digital Age

Tue, 12/12/2017 - 10:20

NEW YORK, Dec. 12, 2017 — ACM, the Association for Computing Machinery, has named 54 members ACM Fellows for major contributions in areas including database theory, design automation, information retrieval, multimedia computing and network security. The accomplishments of the 2017 ACM Fellows lead to transformations in science and society. Their achievements play a crucial role in the global economy, as well as how we live and work every day.

“To be selected as a Fellow is to join our most renowned member grade and an elite group that represents less than 1 percent of ACM’s overall membership,” explains ACM President Vicki L. Hanson. “The Fellows program allows us to shine a light on landmark contributions to computing, as well as the men and women whose tireless efforts, dedication, and inspiration are responsible for groundbreaking work that improves our lives in so many ways.”

Underscoring ACM’s global reach, the 2017 Fellows hail from universities, companies and research centers in China, Denmark, Germany, Hong Kong, Switzerland, the United Kingdom and the United States.

The 2017 Fellows have been cited for numerous contributions in areas including artificial intelligence, big data, computer architecture, computer graphics, high performance computing, human-computer interaction, sensor networks, wireless networking and theoretical computer science.

ACM will formally recognize its 2017 Fellows at the annual Awards Banquet, to be held in San Francisco on June 23, 2018. Additional information about the 2017 ACM Fellows, the awards event, as well as previous ACM Fellows and award winners, is available at http://awards.acm.org/.

2017 ACM Fellows

Lars Birkedal
Aarhus University
For contributions to the semantic and logical foundations of compilers and program verification systems

Edouard Bugnion
EPFL
For contributions to virtual machines

Margaret Burnett
Oregon State University
For contributions to end-user software engineering, understanding gender biases in software, and broadening participation in computing

Shih-Fu Chang
Columbia University
For contributions to large-scale multimedia content recognition and multimedia information retrieval

Edith Cohen
Google Research
For contributions to the design of efficient algorithms for networking and big data

Dorin Comaniciu
Siemens Healthcare
For contributions to machine intelligence, diagnostic imaging, image-guided interventions, and computer vision

Susan M. Dray
Dray & Associates
For co-founding ACM SIGCHI and disseminating exemplary user experience design and evaluation practices worldwide

Edward A. Fox
Virginia Tech
For contributions in information retrieval and digital libraries

Richard M. Fujimoto
Georgia Institute of Technology
For contributions to parallel and distributed discrete event simulation

Shafi Goldwasser  
Massachusetts Institute of Technology
For transformative work that laid the complexity-theoretic foundations for the science of cryptography

Carla P. Gomes  
Cornell University
For establishing the field of computational sustainability, and for foundational contributions to artificial intelligence

Martin Grohe 
RWTH Aachen University
For contributions to logic in computer science, database theory, algorithms, and computational complexity

Aarti Gupta 
Princeton University
For contributions to system analysis and verification techniques and their transfer to industrial practice

Venkatesan Guruswami
Carnegie Mellon University
For contributions to algorithmic coding theory, pseudorandomness and the complexity of approximate optimization

Dan Gusfield
University of California, Davis
For contributions to combinatorial optimization and to algorithmic computational biology

Gregory D. Hager
Johns Hopkins University
For contributions to vision-based robotics and to computer-enhanced interventional medicine

Steven Michael Hand
Google
For contributions to virtual machines and cloud computing

Mor Harchol-Balter 
Carnegie Mellon University
For contributions to performance modeling and analysis of distributed computing systems

Laxmikant Kale 
University of Illinois at Urbana-Champaign
For development of new parallel programming techniques and their deployment in high performance computing applications

Michael Kass
NVIDIA
For contributions to computer vision and computer graphics, particularly optimization and simulation

Angelos Dennis Keromytis
DARPA
For contributions to the theory and practice of systems and network security

Carl Kesselman 
University of Southern California
For contributions to high-performance computing, distributed systems, and scientific data management

Edward Knightly 
Rice University
For contributions to multi-user wireless LANs, wireless networks for underserved regions, and cross-layer wireless networking

Craig Knoblock 
University of Southern California
For contributions to artificial intelligence, semantic web, and semantic data integration

Insup Lee
University of Pennsylvania
For theoretical and practical contributions to compositional real-time scheduling and runtime verification

Wenke Lee
Georgia Institute of Technology
For contributions to systems and network security, intrusion and anomaly detection, and malware analysis

Li Erran Li
Uber Advanced Technologies Group
For contributions to the design and analysis of wireless networks, improving architectures, throughput, and analytics

Gabriel H. Loh
Advanced Micro Devices, Inc.
For contributions to die-stacking technologies in computer architecture

Tomás Lozano-Pérez
Massachusetts Institute of Technology

For contributions to robotics, and motion planning, geometric algorithms, and their applications

Clifford A. Lynch
Coalition for Networked Information
For contributions to library automation, information retrieval, scholarly communication, and information policy

Yi Ma
University of California, Berkeley
For contributions to theory and application of low-dimensional models for computer vision and pattern recognition

Andrew K. McCallum
University of Massachusetts at Amherst
For contributions to machine learning with structured data, and innovations in scientific communication

Silvio Micali
Massachusetts Institute of Technology
For transformative work that laid the complexity-theoretic foundations for the science of cryptography

Andreas Moshovos 
University of Toronto
For contributions to high-performance architecture including memory dependence prediction and snooping coherence

Gail C. Murphy
The University of British Columbia
For contributions to recommenders for software engineering and to program comprehension

Onur Mutlu
ETH Zurich
For contributions to computer architecture research, especially in memory systems

Nuria Oliver
Vodafone/Data-Pop Alliance
For contributions in probabilistic multimodal models of human behavior and uses in intelligent, interactive systems

Balaji Prabhakar 
Stanford University
For developing algorithms and systems for large-scale data center networks and societal networks

Tal Rabin
IBM Research
For contributions to foundations of cryptography, including multi-party computations, signatures, and threshold and proactive protocol design

K. K. Ramakrishnan
University of California, Riverside 
For contributions to congestion control, operating system support for networks and virtual private networks

Ravi Ramamoorthi
University of California San Diego 
For contributions to computer graphics rendering and physics-based computer vision

Yvonne Rogers  
University College London
For contributions to human-computer interaction and the design of human-centered technology

Yong Rui  
Lenovo Group
For contributions to image, video and multimedia analysis, understanding and retrieval

Bernhard Schölkopf
Max Planck Institute for Intelligent Systems
For contributions to the theory and practice of machine learning

Steven M. Seitz
University of Washington, Seattle
For contributions to computer vision and computer graphics

Michael Sipser
Massachusetts Institute of Technology
For contributions to computational complexity, particularly randomized computation and circuit complexity

Anand Sivasubramaniam
Penn State University
For contributions to power management of datacenters and high-end computer systems

Mani B. Srivistava
University of California, Los Angeles
For contributions to sensor networks, mobile personal sensing, and cyber-physical systems

Alexander Vardy
University of California San Diego
For contributions to the theory and practice of error-correcting codes and their study in complexity theory

Geoffrey M. Voelker
University of California San Diego
For contributions to empirical measurement and analysis in systems, networking and security

Martin D. F. Wong
University of Illinois at Urbana-Champaign
For contributions to the algorithmic aspects of electronic design automation (EDA)

Qiang Yang
Hong Kong University of Science and Technology
For contributions to artificial intelligence and data mining

ChengXiang Zhai
University of Illinois at Urbana-Champaign
For contributions to information retrieval and text data mining

Aidong Zhang
State University of New York at Buffalo
For contributions to bioinformatics and data mining

About ACM

ACM, the Association for Computing Machinery (www.acm.org) is the world’s largest educational and scientific computing society, uniting computing educators, researchers and professionals to inspire dialogue, share resources and address the field’s challenges. ACM strengthens the computing profession’s collective voice through strong leadership, promotion of the highest standards, and recognition of technical excellence.  ACM supports the professional growth of its members by providing opportunities for life-long learning, career development, and professional networking.

About the ACM Fellows Program

The ACM Fellows Program (http://awards.acm.org/fellow/) initiated in 1993, celebrates the exceptional contributions of the leading members in the computing field. These individuals have helped to enlighten researchers, developers, practitioners and end users of information technology throughout the world. The new ACM Fellows join a distinguished list of colleagues to whom ACM and its members look for guidance and leadership in computing and information technology.

Source: ACM

The post ACM Recognizes 2017 Fellows for Advancing Technology in the Digital Age appeared first on HPCwire.

Tencent Cloud Adopts Mellanox Interconnect Solutions for HPC and AI Cloud Offering

Tue, 12/12/2017 - 09:33

SUNNYVALE, Calif. & YOKNEAM, Israel, Dec. 12, 2017 — Mellanox Technologies, Ltd. (NASDAQ: MLNX), a leading supplier of high-performance, end-to-end smart interconnect solutions for data center servers and storage systems, today announced that Tencent Cloud has adopted Mellanox interconnect solutions for its high-performance computing (HPC) and artificial intelligence (AI) public cloud offering. TencentCloud is a secure, reliable and high-performance public cloud service that integrates Tencent’s infrastructure capabilities with the advantages of a massive-user platform and ecosystem.

The Tencent Cloud infrastructure leverages Mellanox Ethernet and InfiniBand adapters, switches and cables to deliver advanced public cloud services. By taking advantage of Mellanox RDMA, in-network computing and other interconnect acceleration engines, Tencent Cloud can now offer high-performance computing services, as required by its users, to develop advanced applications and offer new services.

“Tencent Cloud is utilizing Mellanox interconnect and applications acceleration technology to help companies develop their next generation products and offer new and intelligent services,” said Wang Huixing, vice president of Tencent Cloud. “We are excited to work with Mellanox to integrate its world-leading interconnect technologies into our public cloud offerings, and plan to continue to scale our infrastructure product lines to meet the growing needs of our customers.”

“We are proud to partner with Tencent Cloud, who is leveraging our advanced interconnect technology to help build a leading high-performance computing and artificial intelligence-based public cloud infrastructure,” said Amir Prescher, senior vice president of business development at Mellanox Technologies. “Through Tencent Cloud, companies will benefit from Mellanox’s technology to build new products and services that can leverage faster and more efficient data analysis. We look forward to continuing to work with Tencent and expanding the use of Mellanox solutions in its cloud offering.”

Mellanox interconnect solutions deliver the highest efficiency for high-performance computing, artificial intelligence, cloud, storage, and other applications.

About Mellanox

Mellanox Technologies (NASDAQ: MLNX) is a leading supplier of end-to-end InfiniBand and Ethernet smart interconnect solutions and services for servers and storage. Mellanox interconnect solutions increase data center efficiency by providing the highest throughput and lowest latency, delivering data faster to applications and unlocking system performance capability. Mellanox offers a choice of fast interconnect products: adapters, switches, software and silicon that accelerate application runtime and maximize business results for a wide range of markets including high-performance computing, enterprise data centers, Web 2.0, cloud, storage and financial services. More information is available at: www.mellanox.com.

About Tencent Cloud

Tencent Cloud is a leading global cloud service provider. A product of Tencent, Tencent Cloud was built with the expertise of teams who created innovative services like QQ, WeChat and Qzone. Tencent Cloud provides integrated cloud services such as IaaS, PaaS and SaaS, and is a one-stop service for enterprises seeking to adopt public cloud, hybrid cloud, private cloud and cloud-based financial services. It is also a pioneer in cutting edge web technologies such as Cloud Image, facial recognition, big data analytics, machine learning, audio/video technology and security protection. Tencent Cloud delivers integrated industry solutions for gaming, finance, e-commerce, tourism, online-to-offline services, governments, healthcare, online education, and smart hardware. It also provides general solutions with different functions, including online video, website set-up, hybrid cloud, big data, the WeChat eco-system and more. For more information, please visit https://www.qcloud.com/.

Source: Mellanox

The post Tencent Cloud Adopts Mellanox Interconnect Solutions for HPC and AI Cloud Offering appeared first on HPCwire.

ESnet Now Moving More Than 1 Petabyte/wk

Tue, 12/12/2017 - 09:20

Optimizing ESnet (Energy Sciences Network), the world’s fastest network for science, is an ongoing process. Recently a two-year collaboration by ESnet users – the Petascale DTN Project – achieved its ambitious goal to deliver sustained data transfers at over the target rate of 1 petabyte per week. ESnet is managed by Lawrence Berkeley National Laboratory for the Department of Energy.

During the past two years ESnet engineers have been working with staff at DOE labs to fine tune the specially configured systems called data transfer nodes (DTNs) that move data in and out of the National Energy Research Scientific Computing Center (NERSC) at LBNL and the leadership computing facilities at Argonne National Laboratory and Oak Ridge National Laboratory. A good article describing the ESnet project (ESnet’s Petascale DTN project speeds up data transfers between leading HPC centers) was posted yesterday on Phys.org.

A variety of software and hardware upgrades and expansion were required to achieve the speedup. Here are two examples taken from the article:

  • At NERSC, the DTN project resulted in adding eight more nodes, tripling the number, in order achieve enough internal bandwidth to meet the project’s goals. “It’s a fairly complicated thing to do,” said Damian Hazen, head of NERSC’s Storage Systems Group. “It involves adding infrastructure and tuning as we connected our border routers to internal routers to the switches connected to the DTNs. Then we needed to install the software, get rid of some bugs and tune the entire system for optimal performance.”
  • Oak Ridge Leadership Computing Facility now has 28 transfer nodes in production on 40-Gigabit Ethernet. The nodes are deployed under a new model—a diskless boot—which makes it easy for OLCF staff to move resources around, reallocating as needed to respond to users’ needs. “The Petascale DTN project basically helped us increase the ‘horsepower under the hood’ of network services we provide and make them more resilient,” said Jason Anderson, an HPC UNIX/storage systems administrator at OLCF. “For example, we recently moved 12TB of science data from OLCF to NCSA in less than 30 minutes. That’s fast!”

The Petascale DTN collaboration also includes the National Center for Supercomputing Applications (NCSA) at the University of Illinois in Urbana-Champaign, funded by the National Science Foundation (NSF). Together, the collaboration aims to achieve regular disk-to-disk, end-to-end transfer rates of one petabyte per week between major facilities, which translates to achievable throughput rates of about 15 Gbps on real world science data sets. The number of sites with this base capability is also expanding, with Brookhaven National Laboratory in New York now testing its transfer capabilities with encouraging results. Future plans including bringing the NSF-funded San Diego Supercomputer Center and other big data sites into the mix.

Performance measurements from November 2017 at the end of the Petascale DTN project. All of the sites met or exceed project goals. Credit: Eli Dart, ESnet

“This increase in data transfer capability benefits projects across the DOE mission science portfolio” said Eli Dart, an ESnet network engineer and leader of the project. “HPC facilities are central to many collaborations, and they are becoming more important to more scientists as data rates and volumes increase. The ability to move data in and out of HPC facilities at scale is critical to the success of an ever-growing set of projects.”

Link to full Phys.org article: https://phys.org/news/2017-12-esnet-petascale-dtn-hpc-centers.html

The post ESnet Now Moving More Than 1 Petabyte/wk appeared first on HPCwire.

Quantum Unveils Scale-out NAS for High-Value and Data-Intensive Workloads

Tue, 12/12/2017 - 08:51

SAN JOSE, Calif., Dec. 12, 2017 — Quantum Corp. (NYSE: QTM) today announced Xcellis Scale-out NAS, the industry’s first workflow storage appliance to provide the management capabilities and robust features of enterprise scale-out NAS with the cost-effective scaling organizations need to address modern data growth. It delivers greater than 3X the performance of competitive enterprise NAS offerings and, with integrated storage tiering, an end-to-end solution can cost as little as 1/10 that of alternative enterprise NAS solutions with the same capacity and performance. This combination makes Xcellis Scale-out NAS unique in comprehensively addressing the needs of high-value data environments where the organization’s revenue and products are all built around data.

Unified Unstructured Data at Scale 

Many IoT, media and entertainmentlife sciences, manufacturing, video surveillance and enterprise high-performance computing (HPC) environments are outgrowing traditional enterprise NAS. Users have typically turned to scale-out NAS over the past decade as an alternative but are finding that scaling capacity, integrating cloud strategies and sharing data are afterthoughts or not even possible with the solutions they’ve adopted. Unlike enterprise IT workloads, data in high-value workload environments is constantly growing on every axis — ingest, processing, analysis, distribution, archive. These environments require storage solutions with the management and features of enterprise NAS, but which can also cost-effectively scale performance and capacity. Leveraging Quantum’s industry-leading StorNext® parallel file system and data management platform, Xcellis Scale-out NAS offers industry-leading performance, scalability and management benefits for organizations with high-value workloads:

  • Cost-Effective Scaling of Performance and Capacity: Clusters can scale performance and capacity together or independently to reach hundreds of petabytes in capacity and terabytes per second in performance. A single client (SMB, NFS or high-performance client) can achieve over 3X the performance of competitive scale-out NAS offerings with multiple clients scaling a single cluster’s bandwidth to over a terabyte per second. In addition, an end-to-end solution with Xcellis has been shown to manage petabytes of data in a simplified workflow incorporating tape or cloud that provides greater performance than leading NAS-only alternatives for as little as a tenth of the cost.
  • Advanced Features and Flexible Management: With simple installation and setup, a modern administrative single-screen interface provides in-depth monitoring, alerting and management functions as well as rapid scanning and search capabilities that tame large data repositories. Xcellis Scale-out NAS is designed to integrate with the highest performance Ethernet networks through SMB and NFS interfaces and offers the flexibility to also support high-performance block storage in the same converged solution.
  • Lifecycle, Location and Cost Management: Xcellis Scale-out NAS leverages more than 15 years of data management experience built into StorNext. Xcellis data management provides automatic tiering between SSD, disk, tape, object storage and public cloud. Copies can be created for content distribution, collaboration, data protection and disaster recovery.

Artificial Intelligence With Xcellis 

Xcellis Scale-out NAS is the industry’s only NAS solution with integrated artificial intelligence (AI) capabilities that enable customers to create more value from new and existing data. It can actively interrogate data across multiple axes to uncover events, objects, faces, words and sentiments, automatically generating custom metadata that unlocks new possibilities for using stored assets.

Availability

Xcellis Scale-out NAS will be generally available this month with entry configurations and those leveraging tiering starting at under $100 per terabyte (raw).

About Quantum 

Quantum is a leading expert in scale-out tiered storage, archive and data protection. The company’s StorNext platform powers modern high-performance workflows, enabling seamless, real-time collaboration and keeping content readily accessible for future use and remonetization. More than 100,000 customers have trusted Quantum to address their most demanding content workflow needs, including large government agencies, broadcasters, research institutions and commercial enterprises. With Quantum, customers have the end-to-end storage platform they need to manage assets from ingest through finishing and into delivery and long-term preservation. See how at www.quantum.com/customerstories.

Source: Quantum

The post Quantum Unveils Scale-out NAS for High-Value and Data-Intensive Workloads appeared first on HPCwire.

HPC-as-a-Service Finds Toehold in Iceland

Mon, 12/11/2017 - 14:20

While high-demand workloads (e.g., bitcoin mining) can overheat data center cooling capabilities, at least one data center infrastructure provider has announced an HPC-as-a-service offering that features 100 percent free and zero-carbon cooling.

Verne Global, a company seemingly intent on converting Iceland into a gigantic, renewably powered data center facility, has announce hpcDIRECT,  a scalable, bare metal service designed to support power-intensive high performance computing applications. Finding initial markets in the financial services, manufacturing (particularly automotive) and scientific research verticals, hpcDIRECT is powered by the island country’s abundant supply of hydroelectric, geothermal and, to a lesser degree, wind energy that the company says delivers 60 percent savings on power costs.

The launch follows Verne’s a late-October announcement that it had completed a 12.4-Tbps upgrade to the Greenland Connect subsea cable system with three 100-Gpbs connection to New York, lowering latency and delivering, according to Verne, up to 90 percent lower network costs.

hpcDIRECT is a response to customers who “want to consume their HPC in both the traditional sense, where we provide them with colocation capability, power space cooling – the traditional method a data center operator provides services to a customer – and then also to provide a next layer in the technology stack…the hardware and the orchestration of that hardware,” Dominic Ward, managing director at Verne, told EnterpriseTech.

He said hpcDIRECT is available with no upfront charges and can be provisioned to customers’ size and configuration requirements. hpcDIRECT clusters are built using updated architectures available, including Intel’s Xeon (Skylake) servers, connected with Mellanox EDR InfiniBand.

Source: Verne Global

“By leveraging low-cost, reliable, and 100 percent renewable power at its Keflavik campus, the company holds a rather unique position compared to other providers in the industry that offer services similar to hpcDIRECT,” said Teddy Miller, associate analyst at industry watcher 451 Research. “Verne Global’s new product will appeal particularly to enterprises with corporate sustainability mandates or initiatives. The recent completion of an upgrade to Tele Greenland’s Greenland Connect subsea cable system should also significantly lower latency and network costs between the Keflavik campus and New York City. Verne Global may be small compared to other players in the space, but what it offers its customers is cheap, green and increasingly well-connected.”

Verne said hpcDIRECT is accessible via a range of options, from incremental additions to augment existing high performance computing, to supporting massive processing requirements with petaflops of compute. “This flexibility makes it an ideal solution for applications such as computer-aided engineering, genomic sequencing, molecular modelling, grid computing, artificial intelligence and machine learning” the company said.

Demand drivers in financial services for colocation data center services begin with the industry’s movement to reducing capex expenditures on the balance sheet and toward more efficient opex alternatives. Ward said banks and hedge fund companies typically run compute-intensive inter- and intra-day risk applications, “they often have a core level of compute that they want to augment with a more flexible and scalable solution.”

In the automotive sector, companies typically have CFD and crash simulation software running at high utilization 24/7/365. A service like hpcDIRECT, Ward said, “enables them to increment the compute resource they have for high performance applications on a steady basis.” This avoids time consuming and costly procurement cycles, he said. “We’re able to provide them an augmentation, or a complete replacement, for (their high-performance) resources and step into the demand profile that fits their compute demands.”

The post HPC-as-a-Service Finds Toehold in Iceland appeared first on HPCwire.

Fujitsu Develops WAN Acceleration Technology Utilizing FPGA Accelerators

Mon, 12/11/2017 - 10:37

TOKYO, Dec. 11, 2017 — Fujitsu Laboratories Ltd. today announced the development of WAN acceleration technology that can deliver transfer speeds up to 40Gbps for migration of large volumes of data between clouds, using servers equipped with field-programmable gate arrays (FPGAs).

Connections in wide area networks (WANs) between clouds are moving from 1Gbps lines to 10Gbps lines, but with the recent advance of digital technology, including IoT and AI, there is an even greater demand for faster high-speed data transfers as huge volumes of data are collected in the cloud. Until now the effective transfer speed of WAN connections has been raised using techniques to reduce the volume of data, such as compression and deduplication. However, with WAN lines of 10Gbps there are enormous volumes of data to be processed, and existing WAN acceleration technologies usable in cloud servers have not been able to sufficiently raise the effective transfer rate.

Fujitsu Laboratories has now developed WAN acceleration technology capable of real-time operation even with speeds of 10Gbps or higher. WAN acceleration technology is achieved with a dedicated computational unit specialized for a variety of processing, such as feature value calculations and compression processing, mounted onto an FPGA equipped on a server, and in tandem with this, by enabling highly parallel operation of the computational units by supplying data at the appropriate times based on the predicted completion of each computation.

In a test environment where this technology was deployed on servers that use FPGAs, and where the servers were connected with 10Gbps lines, Fujitsu Laboratories confirmed that this technology achieved effective transfer rates of up to 40Gbps, the highest performance in the industry. With this technology, it has become possible to transfer data at high-speeds between clouds, including data sharing and backups, enabling the creation of next-generation cloud services that share and utilize large volumes of data across a variety of companies and locations.

Fujitsu Laboratories aims to deploy this technology, capable of use in cloud environments, as an application loaded on an FPGA-equipped server. It is continuing evaluations in practical environments with the goal of commercializing this technology during fiscal 2018.

Fujitsu Laboratories will announce details of this technology at the 2017 International Conference on Field-Programmable Technology (FPT 2017), an international conference to be held in Melbourne, Australia on December 11-13.

Development Background

As the cloud has grown in recent years, there has been a movement to increase data and server management and maintenance efficiency by migrating data (i.e., internal documents, design data, and email) that had been managed on internal servers to the cloud. In addition, as shown by the spread in the use of digital technology such as IoT and AI, there are high expectations for the ways that work and business will be transformed by the analysis and use of large volumes of data, including camera images from factories and other on-site locations, and log data from devices. Given this, there has been explosive growth in the volume of data passing through WAN lines between clouds, spurring a need for next-generation WAN acceleration technology capable of huge data transfers at high-speed between clouds.

Issues

WAN acceleration technologies improve effective transfer speeds by reducing the volume of data through compression or deduplication of the data to be transferred. When transferring data at even higher speeds using 10Gbps network lines, the volume of data needing to be processed is so great that the compression and deduplication processing speed in the server bottlenecks. Therefore, in order to improve real-time operation, there is a need for either CPUs that can operate at higher speeds, or for WAN acceleration technology with faster processing speeds.

About the Newly Developed Technology

Fujitsu Laboratories has now developed WAN acceleration technology that can achieve real-time operation usable in the cloud even with speeds of 10Gbps or more, using server-mounted FPGAs as accelerators. Efficient operations with WAN acceleration technology are accomplished by using an FPGA to process a portion of the processing for which the computation is heavy and for which it is difficult to improve processing speed in the CPU, when performing compression or deduplication for WAN acceleration processing, and by efficiently connecting the CPU with the FPGA accelerator. Details of the technology are as follows.

1. FPGA parallelization technology using highly parallel dedicated computational units

Fujitsu Laboratories has developed FPGA parallelization technology that can significantly reduce the processing time required for data compression and deduplication by deploying dedicated computational units specialized for data partitioning, feature value calculation, and lossless compression processing in a FPGA in a highly parallel configuration, and by enabling highly parallel operation of the computational units by delivering data at the appropriate times based on predictions of the completion of each calculation.

2. Technology to optimize the flow of processing between CPU and FPGA

Previously, in determining whether to apply lossless compression to data based on the identification of duplication in that data, it was necessary to read the data twice, both before and after the duplication identification was executed on the FPGA, increasing overhead and preventing the system from delivering sufficient performance. Now, by consolidating the processing handoff onto the FPGA, handling both the preprocessing for duplication identification and the compression processing on the FPGA, and using a processing sequence that controls how the compression processing results are reflected on the CPU based on the results of the duplication identification, this technology reduces the overhead between the CPU and FPGA from reloading the input data and from control exchanges. This reduces the waiting time due to the handoff of data and control between the CPU and FPGA, delivering efficient coordinated operation of the CPU and FPGA accelerator.

Effects

Fujitsu Laboratories deployed this newly developed technology in servers installed with FPGAs, confirming acceleration approximately thirty times the performance of CPU processing alone. Fujitsu Laboratories evaluated the transfer speed for a high volume of data in a test environment where the servers were connected with 10Gbps connections, and in a test simulating the regular backup of data, including documents and video, confirmed that this technology achieved transfer speeds up to 40Gbps, an industry record. This technology has significantly improved data transfer efficiency over WAN connections, enabling high-speed data transfers between clouds, such as data sharing and backups, making possible the creation of next-generation cloud services that share and use large volumes of data between a variety of companies and locations.

Future Plans

Fujitsu Laboratories will continue to evaluate this technology in practical environments, deploying this technology in virtual appliances that can be used in cloud environments. Fujitsu Laboratories aims to make this technology available as a product of Fujitsu Limited during fiscal 2018.

About Fujitsu Laboratories

Founded in 1968 as a wholly owned subsidiary of Fujitsu Limited, Fujitsu Laboratories Ltd. is one of the premier research centers in the world. With a global network of laboratories in Japan, China, the United States and Europe, the organization conducts a wide range of basic and applied research in the areas of Next-generation Services, Computer Servers, Networks, Electronic Devices and Advanced Materials. For more information, please see: http://www.fujitsu.com/jp/group/labs/en/.

About Fujitsu Ltd

Fujitsu is a leading Japanese information and communication technology (ICT) company, offering a full range of technology products, solutions, and services. Approximately 155,000 Fujitsu people support customers in more than 100 countries. We use our experience and the power of ICT to shape the future of society with our customers. Fujitsu Limited (TSE: 6702) reported consolidated revenues of 4.5 trillion yen (US$40 billion) for the fiscal year ended March 31, 2017. For more information, please seehttp://www.fujitsu.com.

Source: Fujitsu Ltd

The post Fujitsu Develops WAN Acceleration Technology Utilizing FPGA Accelerators appeared first on HPCwire.

HPC Iron, Soft, Data, People – It Takes an Ecosystem!

Mon, 12/11/2017 - 09:53

Cutting edge advanced computing hardware (aka big iron) does not stand by itself. These computers are the pinnacle of a myriad of technologies that must be carefully woven together by people to create the computational capabilities that are used to deliver insights into the behaviors of complex systems. This collection of technologies and people has been called the High Performance Computing (HPC) ecosystem. This is an appropriate metaphor because it evokes the complicated nature of the interdependent elements needed to deliver first of a kind computing systems.

The idea of the HPC ecosystem has been around for years and most recently appeared in one of the objectives for the National Strategic Computing Initiative (NSCI). The 4th objective calls for “Increasing the capacity and capability of an enduring national HPC ecosystem.” This leads to the questions of, “what makes up the HPC ecosystem” and why is it so important? Perhaps the more important question is, why does the United States need to be careful about letting its HPC ecosystem diminish?

The heart of the HPC ecosystem is clearly the “big humming boxes” that contain the advanced computing hardware. The rows upon rows of cabinets are the focal point of the electronic components, operating software, and application programs that provide the capabilities that produce the results used to create new scientific and engineering insights that are the real purpose of the HPC ecosystem. However, it is misleading to think that any one computer at any one time is sufficient to make up an ecosystem. Rather, the HPC ecosystem requires a continuous pipeline of computer hardware and software. It is that continuous flow of developing technologies that keeps HPC progressing on the cutting edge.

The hardware element of the pipeline includes systems and components that are under development, but are not currently available. This includes the basic research that will create the scientific discoveries that enable new approaches to computer designs. The ongoing demand for “cutting edge” systems is important to keep system and component designers pushing the performance envelope. The pipeline also includes the currently installed highest performance systems. These are the systems that are being tested and optimized. Every time a system like this is installed, technology surprises are found that must be identified and accommodated. The hardware pipeline also includes systems on the trailing edge. At this point, the computer hardware is quite stable and allows a focus on developing and optimizing modeling and simulation applications.

One of the greatest challenges of maintaining the HPC ecosystem is recognizing that there are significant financial commitments needed to keep the pipeline filled. There are many examples of organizations that believed that buying a single big computer would make them part of the ecosystem. In those cases, they were right, but only temporarily. Being part of the HPC ecosystem requires being committed to buying the next cutting-edge system based on the lessons learned from the last system.

Another critical element of the HPC ecosystem is software. This generally falls into two categories – software needed to operate the computer (also called middleware or the “stack”) and software that provides insights into end user questions (called applications). Middleware plays the critical role of managing the operations of the hardware systems and enabling the execution of applications software. Middleware includes computer operating systems, file systems and network controllers. This type of software also includes compilers that translate application programs into the machine language that will be executed on hardware. There are quite a number of other pieces of middleware software that include libraries of commonly needed functions, programming tools, performance monitors, and debuggers.

Applications software span a wide range and are as varied as the problems users want to address through computation. Some applications are quick “throwaway” (prototype) attempts to explore potential ways in which computers may be used to address a problem. Other applications software is written, sometimes with different solution methods, to simulate physical behaviors of complex systems. This software will sometimes last for decades and will be progressively improved. An important aspect of these types of applications is the experimental validation data that provide confidence that the results can be trusted. For this type of applications software, setting up the problem that can include finite element mesh generation, populating that mesh with material properties and launching the execution are important parts of the ecosystem. Other elements of usability of application software include the computers, software, and displays that allow users to visualize and explore simulation results.

Data is yet another essential element of the HPC ecosystem. Data is the lifeblood in the circulatory system that flows through the system to keep it doing useful things. The HPC ecosystem includes systems that hold and move data from one element to another. Hardware aspects of the data system include memory, storage devices, and networking. Also software device drivers and file systems are needed to keep track of the data. With the growing trend to add machine learning and artificial intelligence to the HPC ecosystem, its ability to process and productively use data are becoming increasingly significant.

Finally, and most importantly, trained and highly skilled people are an essential part of the HPC ecosystem. Just like computing systems, these people make up a “pipeline” that starts in elementary school and continues through undergraduate and then advanced degrees. Attracting and educating these people in computing technologies is critical. Another important part of the people pipeline of the HPC ecosystem are the jobs offered by academia, national labs, government, and industry. These professional experiences provide the opportunities needed to practice and hone HPC skills.

The origins of the United States’ HPC ecosystem dates back to the decision by the U.S. Army Research Lab to procure an electronic computer to calculate ballistic tables for its artillery during World War II (i.e. ENIAC). That event led to finding and training the people, who in many cases were women, to program and operate the computer. The ENIAC was just the start of the nation’s significant investment in hardware, middleware software, and applications. However, just because the United States was the first does not mean that it was alone. Europe and Japan also have robust HPC ecosystems for years and most recently China has determinedly set out to create one of their own.

The United States and other countries made the necessary investments in their HPC ecosystems because they understood the strategic advantages that staying at the cutting edge of computing provides. These well-document advantages apply to many areas that include: national security, discovery science, economic competitiveness, energy security and curing diseases.

The challenge of maintaining the HPC ecosystem is that, just like a natural ecosystem, the HPC version can be threatened by becoming too narrow and lacking diversity. This applies to the hardware, middleware, and applications software. Betting on just a few types of technologies can be disastrous if one approach fails. Diversity also means having and using a healthy range of systems that covers the highest performance cutting edge systems to wide deployment of mid and low-end production systems. Another aspect of diversity is the range of applications that can productively use on advanced computing resources.

Perhaps the greatest challenge to an ecosystem is complacency and assuming that it, and the necessary people, will always be there. This can take the form of an attitude that it is good enough to become a HPC technology follower and acceptable to purchase HPC systems and services from other nations. Once a HPC ecosystem has been lost, it is not clear if it can be regained. Having a robust HPC ecosystem can last for decades, through many “half lives” of hardware. A healthy ecosystem allows puts countries in a leadership position and this means the ability to influence HPC technologies in ways that best serve their strategic goals. Happily, the 4th NSCI objective signals that the United States understands these challenges and the importance of maintaining a healthy HPC ecosystem.

About the Author

Alex Larzelere is a senior fellow at the U.S. Council on Competitiveness, the president of Larzelere & Associates Consulting and HPCwire’s policy editor. He is currently a technologist, speaker and author on a number of disruptive technologies that include: advanced modeling and simulation; high performance computing; artificial intelligence; the Internet of Things; and additive manufacturing. Alex’s career has included time in federal service (working closely with DOE national labs), private industry, and as founder of a small business. Throughout that time, he led programs that implemented the use of cutting edge advanced computing technologies to enable high resolution, multi-physics simulations of complex physical systems. Alex is the author of “Delivering Insight: The History of the Accelerated Strategic Computing Initiative (ASCI).”

The post HPC Iron, Soft, Data, People – It Takes an Ecosystem! appeared first on HPCwire.

MareNostrum 4 Chosen as ‘Most Beautiful Data Center’

Mon, 12/11/2017 - 09:28

BARCELONA, Dec. 11, 2017 — MareNostrum 4 supercomputer has been chosen as the winner of the Most Beautiful Data Center in the world Prize, hosted by the Datacenter Dynamics (DCD) Company.

There are 15 prizes in different categories, besides the prize for the most beautiful data centre, which is elected by popular vote. MareNostrum 4 competed with such impressive facilities as the Switch Pyramid in Michigan, the Bahnhof Pionen in Stockholm or the Norwegian Green Mountain. BSC supercomputer has prevailed for its particular location, inside the chapel of Torre Girona, located in the North Campus of the Universitat Politècnica de Catalunya (UPC).

The awards ceremony took place on December 7th in London and both Mateo Valero, BSC Director, and Sergi Girona, Operations department Director, received the prize.

About MareNostrum 4

MareNostrum is the generic name used by BSC to refer to the different upgrades of its most emblematic supercomputer, the most powerful in Spain.  The first version was installed in 2005, and the fourth version is currently in operation.

MareNostrum 4 began operations last July, and according to the latest call of the Top500 list, it ranks the 16th position among the highest performing supercomputers. Currently, MareNostrum provides 11.1 Petaflops of processing power – that is, the capacity to perform 11.1 x (1015) operations per second– to scientific production and innovation. This capacity will be increased soon thanks to the installation of new clusters, featuring emerging technologies, which are currently being developed in USA and Japan.

Aside from being the most beautiful, MareNostrum has been dubbed the most interesting supercomputer in the world due to the heterogeneity of the architecture it will include once installation of the supercomputer is complete. Its total speed will be 13.7 Petaflops. Its main memory is of 390 Terabytes and it has the capacity to store 14 Petabytes (14 million Gigabytes) of data. A high-speed network connects all the components in the supercomputer to one another.

MareNostrum 4 has been funded by the Economy, Industry and Competitiveness Ministry of the Spanish Government and was awarded by public tender to IBM Company, which integrated into a single machine its own technologies together with the ones developed by Lenovo, Intel and Fujitsu.

About Barcelona Supercomputing Center

Barcelona Supercomputing Center (BSC) is the national supercomputing centre in Spain. BSC specialises in High Performance Computing (HPC) and its mission is two-fold: to provide infrastructure and supercomputing services to European scientists, and to generate knowledge and technology to transfer to business and society.

Source: Barcelona Supercomputing Center

The post MareNostrum 4 Chosen as ‘Most Beautiful Data Center’ appeared first on HPCwire.

Pages